Avoid bus jamming

To assure network-wide data consistency, each node in a CAN network has the right to terminate any CAN message interpreted as faulty. This also applies to a CAN node that erroneously interprets correct CAN messages as faulty. To prevent jamming up the transmission medium, the CAN protocol specifies error tracking that allows CAN nodes to distinguish between occasionally occurring disturbances and persistent ones.


Consequently, each CAN controller has a TEC (Transmit Error Counter) and a REC (Receive Error Counter). In case of successful transmission of a data or remote frame, the relevant error counter is decremented (TEC=TEC-1; REC=REC-1). Detection and subsequent transmission of a error flag causes the relevant error counter to be incremented according to certain rules. For the sender the following rule applies: TEC=TEC+8. Error-detecting receivers initially increment their REC by one unit (REC=REC+1). For the error causing receiver: REC=REC+8.

Error Active

Depending on the specific error count, a CAN controller handles switching of the error state. After the start, a CAN controller assumes the normal state Error Active. In this state, the CAN controller sends six dominant bits (active error flag) after detecting an error. When a limit is exceeded (TEC>127; REC>127), the CAN controllers switch over to the “Error Passive” state.

Error Passive

CAN controllers in the Error Passive state can only indicate a detected error by sending six homogeneous recessive bits. This prevents the error-detecting receivers from globalizing detected errors. In addition, when sending two consecutive data or remote frames, CAN controllers that are in the “Error Passive” state must wait the “Suspend Transmission Time” (8 bits).

Bus Off

If a CAN controller fails or if there are extreme accumulations of errors, a state transition is made to the Bus Off state. The CAN controller disconnects from the CAN bus. The Bus-Off state can only be exited by intervention of the host (with a mandatory waiting time of 128 x 11 bits) or by a hardware reset.

Last modified: Wednesday, 22 September 2021, 4:12 PM